Integrated Circuit (IC) devices typically include numerous transistors that are fabricated on, for example, silicon wafers. There are several types of IC devices, including Application Specific Integrated Circuit (ASIC) devices and Programmable Logic Devices (PLDs). ASIC devices include logic elements connected by dedicated (hard-wired) interconnect lines such that each ASIC device performs a predetermined (fixed) logic operation. ASIC devices include dedicated input pins for receiving input signals, and dedicated output pins (terminals) for transmitting output signals to other devices. The function (input or output) of each pin of an ASIC device is fixed during production. In contrast to ASIC devices, PLDs include undedicated (user-configurable) logic elements and interconnect resources that are programmable to implement user-defined logic operations (that is, a user's circuit design). The function (input or output) of each data pin on a PLD is typically determined after production. To provide this optional functionality, PLD pins are typically connected to the logic elements and interconnect resources through user programmable input/output (I/O) circuits. Pins that are connected to these I/O circuits are referred to as I/O pins.
FIG. 1 is a diagram showing a portion of an I/O circuit 100 that is used in known PLDS. I/O circuit 100 is programmed to operate in either an input mode or an output mode by an output enable (OE) signal that is generated by the internal logic circuitry or transmitted on a global bus line of a PLD. The OE signal is transmitted to the first input terminal of a two-input NAND gate 110, and through an inverter 120 to the first input terminal of a two-input NOR gate 130. I/O circuit 100 also receives data output (DATA OUT) signals from internal circuitry of a PLD (not shown). The DATA OUT signals are transmitted to the second input terminals of NAND gate 110 and NOR gate 130. The output signal of NAND gate 110 is transmitted on line 115 to the gate of a PMOS pull-up transistor 140 that is connected between Vcc and a PLD I/O pin 160. The output signal of NOR gate 130 is transmitted on line 135 to the gate of an NMOS pull-down transistor 150 that is connected between I/O pin 160 and ground. I/O pin 160 is also connected through an input buffer 170, which includes serially-connected inverters 172 and 174, to a DATA IN line that transmits data input signals to the internal circuitry of the PLD (not shown).
As mentioned above, I/O circuit 100 operates in two modes: an output mode in which I/O pin 160 is used for transmitting output signals from the PLD, and an input mode in which I/O pin 160 is used for receiving input signals from an external source or device, and passing the input signals to the internal portions of the PLD. In the output mode, a high OE signal causes pull-up transistor 140 and pull-down transistor 150 to generate high (Vcc) and low (0V or ground) signals on I/O pin 160 in response to DATA OUT signals. In the input mode, a low OE signal tri-states the output driver formed by PMOS pull-up transistor 140 and NMOS pull-down transistor 150, thereby disconnecting the DATA OUT line from I/O pin 160. That is, the low OE signal causes NAND gate 110 and NOR gate 130 to generate high and low output signals, respectively, regardless of any DATA OUT signal. The high signal from NAND gate 110 and the low signal from NOR gate 130 respectively maintain pull-up transistor 140 and pull-down transistor 150 in off states. With pull-up transistor 140 and pull-down transistor 150 turned off, input signals pass unimpeded from I/O pin 160 through input buffer 170 to the internal portions of the PLD on the DATA IN line.
As is the case with the majority of IC manufacturers, PLD manufacturers are constantly striving to improve the performance and reduce the cost of the devices they produce. The primary means of achieving these two very important goals is through migration to processing technologies with ever-smaller geometries. Semiconductor devices are commonly produced using, for example, a 0.5 micron (um) process technology, where "0.5 micron" refers to the minimum channel length of transistors that can be reliably produced with that particular technology. In addition to reduced channel lengths, more advanced processes typically have significant reductions in other geometries as well, such as metal pitch, diffusion spacing, gate oxide thickness, etc. These smaller geometries naturally result in devices with smaller die size, which can substantially reduce the per-die cost of manufacturing. Typically, the smaller process dimensions also result in significant performance improvements. Gate and interconnect delays are normally reduced as a product of enhanced transistor performance and diminished parasitic loading.
Currently, many semiconductor manufacturers are migrating from industry-standard 0.6 and 0.5 um technologies to advanced 0.35 um and 0.25 um technologies. IC devices produced using 0.6 and 0.5 um technologies typically operated on 5V power supplies. However, in the advanced process technologies, the gate oxide thickness and channel length of the transistors is normally reduced to a point where 3.3V supplies (or lower) will be commonly used. I/O circuit 100 provides reliable operation in 5V PLDS, but can cause problems when utilized in 3.3V PLDS. All PLDs are typically incorporated into systems in which they communicate with (i.e., send output signals to and receive input signals from) other IC devices, such as TTL or CMOS logic devices. When a PLD and all other devices in such a system operate on a common supply (e.g., 5V or 3.3V), I/O circuit 100 reliably functions in both the input mode and the output mode. For example, when a 5V PLD (i.e., Vcc of the PLD is 5V) is incorporated into a system including TTL or CMOS devices, the signals received at I/O pin 160 associated with a particular I/O circuit 100 does not exceed 5.5 volts. Therefore, the voltage differential (.DELTA.V) across pull-up transistor 140 does not exceed one P-channel threshold voltage (Vtp) above Vcc, so pull-up transistor 140 remains off. Similarly, when a 3.3V PLD is incorporated into a system including only 3.3V devices, pull-up transistor 140 is not subjected to a .DELTA.V that exceeds one Vtp above Vcc. However, problems may occur when a 3.3V PLD is incorporated into a system including 5V devices. Of course, a 3.3V PLD can safely drive its own I/O pin in such a system when the I/O pin is being used for data output. However, when the I/O pin of a 3.3V PLD is being driven by a neighboring 5V device (i.e., in the input mode), the 5V signals applied to the I/O pin may damage the transistors of the I/O circuit and/or cause significant current leakage. Damage to I/O circuit 100 is particularly problematic when the 3.3V PLD is produced using advanced 0.35 or smaller process technologies. In this case, pull-up transistor 140, pull-down transistor 150 and input buffer 170 may be damaged by the 5V signal on I/O pin 160 due to their thinner gate oxides and shorter channel lengths that will result in excessive electric fields. Even if a 3.3V PLD is produced using 0.5 um process technologies, 5V signals on I/O pin 160 produce current leakage through pull-up transistor 140. In particular, as shown in FIG. 1, it is common practice to tie the N-well of PMOS pull-up transistor 140 to Vcc (e.g., 3.3V). In this case, when I/O pin 160 is raised to 5V or more, the resulting potential across pull-up transistor 140 forward biases a parasitic diode 180 created by the P-N junction between the I/O pin node and the N-well of PMOS pull-up transistor 140 (i.e., .DELTA.V=1.7V, which is greater that Vtp.apprxeq.0.7V). Forward-biased parasitic diode 180 produces excessive current leakage and causes pull-up transistor 140 to function incorrectly. Finally, even if the N-well of pull-up transistor 140 were not tied to Vcc, a leakage problem would still exist. Specifically, the signal on line 115 that is applied to the gate of pull-up transistor 140 is Vcc (3.3V) in the input mode in order to maintain pull-up transistor 140 in an off state. However, if the voltage at I/O pin 160 exceeds the voltage on line 115 by one p-channel threshold voltage (where Vtp.apprxeq.0.7V), pull-up transistor 140 will turn on and sink I/O pin 160 into Vcc, again creating excessive leakage.
What is needed is an improved low voltage I/O circuit with a high voltage tolerance that avoids the above-mentioned problems associated with the prior art I/O circuits, and is implemented using processes that are consistent with the fabrication of other portions of the IC or PLD upon which the I/O circuit is formed.